Segmentation: a technique for adapting high-performance logic ATE to test high-density, high-speed SRAMs

In order to make decoder lines shorter, and thus decrease average access-times to the cells, SRAM designers employ a cascaded, multiple-array structure-instead of building SRAMs as a single `monolithic´ array of cells. By rearranging traditional memory test patterns to take account of the true distribution of decoder branches within the die layout, the test can be focussed on cells which form a single array `segment´, (i.e. cells that share the same row/column decoders). This `segmented´ test pattern requires fewer cycles to execute, and in nearly all cases has at least the same fault coverage as the traditional `monolithic´ version of the test pattern. Additionally, these `segmented´ patterns can be ideally handled by logic test ATE using the modern `per-pin´ resource architecture, to take advantage of the superior accuracy and vector rate of these testers