DocumentCode :
3490498
Title :
SOI DRAM: its features and possibility
Author :
Yamaguchi, Yoshio ; Inoue, Yasuo
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Japan
fYear :
1995
fDate :
3-5 Oct 1995
Firstpage :
122
Lastpage :
124
Abstract :
An SOI DRAM is a candidate for giga-bit scale DRAM with improved data retention characteristics and/or simple capacitor structure achieved by low leakage current, reduced soft error effect and low Cb/Cs ratio. The SOI DRAM is also expected to realize low-voltage memory which will be used in handy systems in a forthcoming multimedia era by reduced junction capacitance and back-gate-bias effect. However, some drawbacks are also suspected owing to floating substrate effects. In the present report, these features are summarized to demonstrate the perspective on SOI DRAM
Keywords :
DRAM chips; VLSI; capacitance; leakage currents; silicon-on-insulator; SOI DRAM; Si; back-gate-bias effect reduction; capacitor structure; data retention characteristics; dynamic RAM; floating substrate effects; giga-bit scale DRAM; junction capacitance reduction; low leakage current; low-voltage memory; soft error effect reduction; Capacitance; Capacitors; Laboratories; Leakage current; Potential well; Random access memory; Subthreshold current; Temperature measurement; Time measurement; Ultra large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 1995. Proceedings., 1995 IEEE International
Conference_Location :
Tucson, AZ
Print_ISBN :
0-7803-2547-8
Type :
conf
DOI :
10.1109/SOI.1995.526491
Filename :
526491
Link To Document :
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