DocumentCode
3490584
Title
An inexpensive method of detecting localised parametric defects in static RAM
Author
Savaria, Y. ; Thibeault, C.
Author_Institution
Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
fYear
1993
fDate
9-10 Aug 1993
Firstpage
90
Lastpage
95
Abstract
The author presents an effective method of testing spot defects causing delay faults in SRAM circuits, without having to perform a full speed test of every single cell in a chip. The method is based on the detection of spot defects through the imbalance they cause to memory cells by transforming the imbalance effect into a permanent error. Such tests may be performed at a low speed, while retaining an excellent ability to detect non-catastrophic spot defects
Keywords
SRAM chips; fault location; integrated circuit testing; SRAM circuits; delay faults; localised parametric defects; memory cells; static RAM; Added delay; Circuit faults; Circuit testing; Delay effects; Driver circuits; Integrated circuit testing; Logic circuits; Logic testing; Performance evaluation; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Testing, 1993., Records of the 1993 IEEE International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-4150-9
Type
conf
DOI
10.1109/MT.1993.263143
Filename
263143
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