Title :
Low Power Sampling Latch for up to 25 Gb/s 2x Oversampling CDR in 90-nm CMOS
Author :
von Buren, G. ; Rodoni, L. ; Kromer, C. ; Jäckel, H. ; Huber, A. ; Morf, T.
Author_Institution :
Electron. Lab., Swiss Fed. Inst. of Technol., Zurich
Abstract :
A sampling latch for full-, half and quarter-rate clock and data recovery circuits at data rates of 12.5 Gb/s, 20 Gb/s and 25 Gb/s, respectively, achieving a bit error rate lower than 10-12 is presented. The circuit is implemented in a 90-nm CMOS technology. The master-slave D-FF including peaking inductors consumes only 1 mW of power and requires a snail area of 30times20 mum2
Keywords :
CMOS integrated circuits; clocks; error statistics; flip-flops; synchronisation; 1 mW; 25 Gbit/s; 90 nm; CMOS technology; bit error rate; clock and data recovery circuits; low power sampling latch; master-slave D-FF; oversampling CDR; peaking inductors; Bandwidth; Bit error rate; CMOS technology; Circuits; Clocks; Laboratories; Latches; Master-slave; Phase detection; Sampling methods;
Conference_Titel :
Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0303-0
DOI :
10.1109/ESSCIR.2006.307542
