DocumentCode
3490645
Title
An optimal march test for locating faults in DRAMs
Author
Shen, Lin ; Cockburn, Bruce F.
Author_Institution
Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
fYear
1993
fDate
9-10 Aug 1993
Firstpage
61
Lastpage
66
Abstract
The authors solve the fault location problem for a realistic fault model that is based on the physical defects and resulting faulty behaviours observed in 4 Mbit DRAMs manufactured by Siemens. Assuming an n×1 DRAM organization, they derive a lower bound of 8n on the length of any march test that locates all of the faults in the fault model. They then propose a march test whose length matches the lower bound, and then show that this test has 100% fault coverage
Keywords
DRAM chips; fault location; integrated circuit testing; 4 Mbit; DRAMs; Siemens; fault location problem; fault model; optimal march test; physical defects; Automata; Capacitors; Failure analysis; Fault detection; Fault diagnosis; Fault location; Random access memory; Read-write memory; Testing; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Testing, 1993., Records of the 1993 IEEE International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-4150-9
Type
conf
DOI
10.1109/MT.1993.263148
Filename
263148
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