Title :
An Alternating Spacer AES Crypto-processor
Author :
Murphy, Julian ; Yakovlev, Alex
Author_Institution :
Sch. of EECE, Newcastle upon Tyne Univ.
Abstract :
An AES crypto-processor has been fabricated to investigate the security properties of an alternating spacer dual-rail logic style and a security based design flow; which introduces a previously unused state in differential power-balancing. The fruits of which offer a tangible solution to information leakage during the life-time of a smartcard´s secret key, whilst crucially keeping the usually expensive costs of increased smartcard security to a minimum: design economics, area and power. Power analysis on the device results in a forty fold increase in the number of power measurements needed to crack the 128-bit secret key over an unmodified and architecturally identical design. Area is only increased by 88% compared to 3-4times in other reported power-balancing methods (Pop, 2005)
Keywords :
microprocessor chips; power measurement; private key cryptography; smart cards; 128 bit; AES crypto-processor; alternating spacer dual-rail logic style; differential power-balancing; information leakage; power analysis; power measurements; power-balancing methods; security based design flow; security properties; smartcard secret key; CMOS logic circuits; Clocks; Cryptography; Energy consumption; Information security; Logic circuits; Logic design; Logic devices; Power measurement; Power system security;
Conference_Titel :
Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0303-0
DOI :
10.1109/ESSCIR.2006.307547
