Title :
On-line and off-line testable design of random access memories
Author :
Subramanian, Siva ; Lala, Parag K.
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
The authors propose a testable design of random access memories (RAM) which facilitates both on-line and off-line testing of the devices. The high density of the memory devices necessitates high speed off-line testing techniques. Critical applications desire on-line testability of these devices. The proposed design partitions the chip into blocks and sets in order to achieve high speed off-line testability as well as on-line testability
Keywords :
automatic testing; design for testability; integrated circuit testing; integrated memory circuits; random-access storage; RAM testing; off-line testing; offline testing; online testing; random access memories; testable design; Circuit faults; Circuit testing; Decoding; Electrical fault detection; Fault detection; Logic circuits; Logic devices; Logic testing; Random access memory; Read-write memory;
Conference_Titel :
Memory Testing, 1993., Records of the 1993 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-4150-9
DOI :
10.1109/MT.1993.263154
