Title :
PLA test pattern generation with orthogonal transform
Author :
Riege, M.W. ; Wolter, S. ; Anheier, W.
Author_Institution :
Electron. Dept., Bremen Univ., Germany
Abstract :
It is known that test pattern generation even for fixed structured realizations of digital circuits, i.e. PLAs is a NP-complete problem. With respect to the growing complexity of integrated circuits, this process has to be optimized to avoid large development and production cycles. The target of the authors´ work is a method (as a part of fault simulation), which speeds up the process of test pattern generation for regular structures as PLAs, ROMs, RAMs and which also reduces time and storage complexity
Keywords :
logic arrays; logic testing; transforms; NP-complete problem; PLA test; RAMs; ROMs; fault simulation; integrated circuits; orthogonal transform; test pattern generation; Boolean functions; Ducts; Equations; Hamming weight; Programmable logic arrays; Test pattern generators;
Conference_Titel :
Memory Testing, 1993., Records of the 1993 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-4150-9
DOI :
10.1109/MT.1993.263156
