Efficient interleaver memory architectures for serial turbo decoding

A practical turbo decoder is usually implemented with a serial decoding architecture for low complexity, where the extrinsic information symbols are stored in the so-called interleaver memory for the next decoding. Either a dual-port (or two ping-pong memories) or a single-port memory can be employed for this memory. The first approach achieves twice the throughput as the second one while spending approximately twice the hardware on the interleaver memory. In this work, two novel architectures are proposed for the interleaver memory design. Both proposed architectures work for any type of random interleavers. Compared with the traditional single-port approach, twice the throughput can be obtained with less than 1% area overhead when applied in third generation CDMA systems. On the other hand, more than 25% area of an entire turbo decoder can be saved compared with the traditional dual-port solution.