Efficient VLSI implementation of modern symmetric block ciphers

In this paper efficient VLSI architectures for three modern symmetric block ciphers RC5-32/12/16, SAFER K-128 and 3WAY are discussed. The connection between algorithm properties and VLSI architectures are described. An exemplary performance analysis and comparison of VLSI architectures for a 0.7 μm CMOS standard cell process are carried out. The results of the work are reusable soft and firm cores, which can be embedded in integrated systems and allow high speed data encryption. One of the developed VLSI architectures for the 3WAY algorithm achieves a data throughput up to 1.6 Gbit/s, which is up to now the highest encryption speed of a sym. block cipher realized in a CMOS process