Title :
Final polish for SOI wafers-surface roughness and TTV degradation
Author :
Pfeiffer, G. ; Fetheroff, S. ; Iyer, S.S.
Author_Institution :
SiBond L.L.C., Hopewell Junction, NY, USA
Abstract :
We have demonstrated a manufacturable final CMP based process to recover the roughness of as-prepared SOI wafers. The roughness achievable is comparable to prime Si bulk wafers and in keeping with Si wafer requirements for ULSI. Concomitant to the process is some TTV degradation. Our process has been tuned to minimize this degradation and to keep it consistent with CMOS/SOI requirements on TTV
Keywords :
integrated circuit manufacture; integrated circuit technology; polishing; silicon-on-insulator; surface topography; BESOI wafers; CMOS/SOI; SOI wafers; Si; TTV degradation; ULSI; bond/etchback SOI; final polish process; kiss polish process; manufacturable final CMP based process; surface roughness; Atomic force microscopy; Atomic measurements; Degradation; Etching; Force measurement; Rough surfaces; Silicon on insulator technology; Surface contamination; Surface roughness; Surface topography;
Conference_Titel :
SOI Conference, 1995. Proceedings., 1995 IEEE International
Conference_Location :
Tucson, AZ
Print_ISBN :
0-7803-2547-8
DOI :
10.1109/SOI.1995.526515
