Title :
Modelling charge-pump delay locked loops
Author :
Aguiav, R.L. ; Santos, Dinis Magalhães
Author_Institution :
Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
Abstract :
This paper presents a new sampled-time model for charge-pump delay locked loops (DLLs). This novel model is used for jitter analysis, extending previous results and providing better insight to jitter transfer mechanisms in DLLs. The model includes both the effects of total line delay and the control loop of the DLL, and is applied to input jitter and internally generated jitter. This model is further extended to handle jitter effects related with the control charge-pump. Conclusions based on this model are finally presented, and confronted with previous knowledge and practical implementations in DLLs
Keywords :
clocks; delay lock loops; timing jitter; charge-pump delay locked loops; control charge-pump; control loop; input jitter; internally generated jitter; jitter analysis; jitter transfer mechanisms; sampled-time model; total line delay; Capacitors; Charge pumps; Circuits; Clocks; Delay lines; Desktop publishing; Detectors; Jitter; Phase detection; Voltage control;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.813235
