Title :
A High Linearity and Fast-Locked PulseWidth Control Loop with Digitally Programmable Output Duty Cycle for Wide Range Operation
Author :
Cheng, Kuo-Hsing ; Su, Cia-Wei ; Chang, Kai-Fei ; Hung, Cheng-Liang ; Yang, Wei-Bin
Author_Institution :
Dept. of Electr. Eng., National Central Univ., Taoyuan
Abstract :
In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18mum CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz
Keywords :
CMOS integrated circuits; integrated circuit testing; phase locked loops; programmable circuits; 0.18 micron; 13.2 ps; 4.8 mW; 50 to 1.3E3 MHz; CMOS process; digital-controlled charge pump; digitally programmable output duty cycle; fast-locked pulsewidth control loop; high linearity pulsewidth control loop; linear control stage; measurement power dissipation; test chip; CMOS process; Charge pumps; Circuit testing; Digital control; Frequency measurement; Linearity; Power dissipation; Power measurement; Semiconductor device measurement; Space vector pulse width modulation;
Conference_Titel :
Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0303-0
DOI :
10.1109/ESSCIR.2006.307560
