A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network

A 1 Gb density, 5.2 Gbps/s/pin data rate GDDR5 SDRAM was developed using 66 nm DRAM process. It uses traditional Core architecture, 8-bit pre-fetch with 16-banks, but the clocking and interface topology are fully changed for operating more than 4 Gbps without using differential signaling. Major barrier to achieving high data bandwidth is the clock jitter. To overcome this limitation, this project utilizes a CML clocking scheme.