A 0.2V 0.44 /spl mu W 20 kHz Analog to Digital /spl Sigma/Δ Modulator with 57 fJ/conversion FoM

Author

Wismar, Ulrik ; Wisland, Dag ; Andreani, Pietro

Author_Institution

Orsted DTU, Denmark Tech. Univ., Lyngby

fYear

2006

fDate

19-21 Sept. 2006

Firstpage

187

Lastpage

190

Abstract

This paper presents a 90 nm CMOS ΣΔ A/D modulator operating with a supply voltage of 0.2 V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequency-modulated intermediate signal, generated in a ring voltage-controlled oscillator. The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4 MHz, for a total power consumption as low as 0.44 μW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 dB.

Keywords

CMOS integrated circuits; sigma-delta modulation; voltage-controlled oscillators; 0.2 V; 0.44 muW; 20 kHz; 3.4 MHz; 50 fJ; 90 nm; CMOS A/D modulator; analog-digital modulator; conversion FoM; sigma-delta modulator; voltage-controlled oscillator; Bandwidth; Digital modulation; Dynamic range; Frequency measurement; Linearity; Power measurement; Sampling methods; Signal generators; Threshold voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European

Conference_Location

Montreux

ISSN

1930-8833

Print_ISBN

1-4244-0303-0

Type

conf

DOI

10.1109/ESSCIR.2006.307562

Filename

4099735