A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range

We present a CT-DeltaSigma modulator operating at a sampling rate of 300 Msps in a 0.18 mum CMOS process. A low power four bit flash ADC and a complementary current-steering DAC are used to reduce power and noise. The opamps used in the active-RC loop filter are deliberately made slow to further reduce current consumption and the resulting loop delay is compensated. The modulator achieves a peak SNR of 67.2 dB in a 15 MHz bandwidth (OSR=10) while dissipating only 20.7 mW from a 1.8 V supply.