A 1.8 V low-power CMOS high-speed four quadrant multiplier with rail-to-rail differential input

Author

Lin, Chi-Hung ; Ismail, Mohammed

Author_Institution

Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA

Volume

1

fYear

1998

fDate

1998

Firstpage

37

Abstract

A low-voltage (⩽3 V) CMOS four quadrant multiplier is introduced which has an almost rail-to-rail differential-input-swing with a low signal-distortion (⩽1% for 1 MHz signal, ⩽7% for 100 MHz signal). The proposed circuit is composed of a pair of rail-to-rail differential-input V-I converters and a pair of voltage-followers. This topology of multiplier results in a high frequency capability with low power consumption. In a 1.2 μm n-well CMOS process, the 3 dB frequency of the multiplier is in a range of 103 MHz. The total power consumption is around 0.5 mW with supply voltage 2 V. The multiplier can operate at a minimum supply voltage of 1.8 V

Keywords

CMOS analogue integrated circuits; analogue multipliers; high-speed integrated circuits; low-power electronics; 0.5 mW; 1.2 micron; 1.8 to 3 V; 103 MHz; differential-input V-I converters; four quadrant multiplier; high frequency capability; high-speed multiplier; low power consumption; low signal-distortion; low-power CMOS multiplier; low-voltage operation; n-well CMOS process; rail-to-rail differential input; voltage-followers; CMOS process; Circuit topology; Distortion; Energy consumption; Frequency; MOS devices; Rail to rail inputs; Threshold voltage; Transconductance; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813266

Filename

813266