A 60GHz digitally controlled phase shifter in CMOS

Author

Yu, Yikun ; Baltus, Peter ; Van Roermund, Arthur ; Jeurissen, Dennis ; De Graauw, Anton ; Van der Heijden, Edwin ; Pijper, Ralf

Author_Institution

Dept. of Electr. Eng., Eindhoven Univ. of Technol., Eindhoven

fYear

2008

fDate

15-19 Sept. 2008

Firstpage

250

Lastpage

253

Abstract

This paper presents a 60 GHz digitally controlled phase shifter in the 65 nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5deg, an average insertion loss of 8.5 to 10.3 dB and a return loss of better than 10 dB from 55 to 65 GHz. The phase shifter occupies an area of only 0.2 mm². To the knowledge of the authors, this is the first 60 GHz digitally controlled phase shifter with a phase resolution of 22.5deg in silicon reported to date. It is well suited for a 60 GHz phased array.

Keywords

CMOS digital integrated circuits; antenna phased arrays; field effect MIMIC; millimetre wave phase shifters; radiocommunication; transmission lines; CMOS technology; differential varactor-loaded transmission-line architecture; digital controlled phase shifter; frequency 60 GHz; high-speed short-range wireless communication; insertion loss; phased array antenna; return loss; CMOS technology; Digital control; Insertion loss; Phase shifters; Phased arrays; Power transmission lines; Propagation losses; Radio frequency; Transmission lines; Varactors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European

Conference_Location

Edinburgh

ISSN

1930-8833

Print_ISBN

978-1-4244-2361-3

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2008.4681839

Filename

4681839