A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS

A high-performance 13 bit current-steering DAC for analog subsystems is implemented in a standard 0.13 mum CMOS technology. A novel dynamic background calibration scheme directly trims the unary DAC-elements in differently weighted segments of the current source array. Interleaved current cells implement an effective RZ- behavior with NRZ output current waveform, which improves the dynamic linearity of the converter by 20 dB at 64 MHz. Clocked at 130 MHz, the converter draws 53 mW from a 1.5 V supply and achieves a SFDR > 73 dB for signal frequencies up to Nyquist. Operated at 300 MS/s with a 3x interpolation filter, the converter consumes 73 mW and achieves a SFDR > 68dB within the signal bandwidth of 50 MHz.