FPGA based prototyping using a target driven FSM partitioning strategy

Author

Feske, K. ; Rülke, St ; Koegst, M.

Author_Institution

Dept. EAS, FhG IIS Erlangen, Dresden, Germany

Volume

1

fYear

1998

fDate

1998

Firstpage

89

Abstract

To enhance efficiency and quality in rapid prototyping we insert a novel high-level optimization approach into a proved design flow. This approach applies a FSM partitioning technique which takes technology-specific features into consideration and performs state encoding simultaneously. Reducing FPGA resources drastically, it assists the designer to get by on the available resources if an ASIC-oriented specification has to re-targeted to a FPGA prototype

Keywords

application specific integrated circuits; circuit CAD; circuit optimisation; encoding; field programmable gate arrays; finite state machines; high level synthesis; integrated circuit design; logic partitioning; rapid prototyping (industrial); ASIC-oriented specification; FPGA based prototyping; FPGA prototype; LUT architecture; high-level optimization approach; rapid prototyping; state encoding; target driven FSM partitioning strategy; technology-specific features; Application specific integrated circuits; Automatic control; Design optimization; Electronic mail; Encoding; Field programmable gate arrays; Hardware; Process design; Prototypes; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813277

Filename

813277