A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability

An extremely low energy/operation, single cycle 32 bit/word, 128 Kbit SRAM is fabricated in 90 nm CMOS. In the 850 MHz boost mode, energy consumption is 8.4 pJ/access. This reduces to 3.6 pJ/access in the normal 480 MHz mode and bottoms out at a very aggressive 2.7 pJ/access in the 240 MHz low power mode. This performance is obtained using novel, digitally tunable sense amplifiers and a tunable timing circuit that cope gracefully with the stochastic variations in the periphery.