A Low Power Embedded SRAM for Wireless Applications

This paper introduces a novel ultra low power SRAM. A large power reduction is obtained by the use of four new techniques that allow for a wider and better trade-off between area, delay and active and passive energy consumption for low power embedded SRAMs. The design targets wireless applications that require a moderate performance and an ultra low power consumption. The implemented design techniques consist of a more efficient memory databus, the exploitation of the dynamic read stability of SRAM cells, a new low swing write technique and a distributed decoder. An 8 KByte 5T SRAM was fabricated in a 0.18mum technology. The measurement results confirm the feasibility and the usefulness of the proposed techniques. A reduction of active power consumption with a factor of 2 is reported as compared to the current state of the art. The results are generalized towards a 32 KByte SRAM