Asynchronous wave pipelines for high throughput datapaths

A novel VLSI pipeline architecture for high-speed clockless computation is proposed. It features gate-level pipelining to maximize throughput and uses dynamic latches to keep the latency low. The most salient property is the asynchronous operation using a modified handshake protocol. Data words are accompanied by associated control signals resembling a local clock and propagate in coherent waves through the logic. As a result one can take advantage of the asynchronous operation and avoid the problems prevalent with global high-speed clocks in synchronous designs. HSpice simulations of an 4-bit adder designed in 0.7 μm CMOS indicate throughput data rates at 1 GHz