Flexible hardware acceleration for nesting problems

Author

Ferreira, J. Canas ; Alves, J. Carlos ; Albuquerque, C. ; Oliveira, José F. ; Ferreira, J. Soeiro ; Matos, J. Silva

Author_Institution

INESC, Porto, Portugal

Volume

1

fYear

1998

fDate

1998

Firstpage

345

Abstract

The nesting (or placement) problem is an NP-hard combinatorial problem with important industrial applications, e.g. in apparel or footwear industry. This paper describes a hardware infrastructure to accelerate the processing of the underlying geometric information. The system consists of an FPGA-based reconfigurable platform enhanced by an ASIC for the processing of irregular polygons. The paper discusses the need for such a platform, establishes the main design guidelines and describes the architecture and modes of operation of both the reconfigurable infrastructure and the dedicated IC

Keywords

application specific integrated circuits; coprocessors; field programmable gate arrays; mathematics computing; reconfigurable architectures; ASIC; FPGA-based reconfigurable platform; NP-hard combinatorial problem; dedicated IC; flexible hardware acceleration; geometric information; irregular polygons; nesting problems; placement problem; reconfigurable hardware infrastructure; Acceleration; Application specific integrated circuits; Benchmark testing; Containers; Footwear industry; Guidelines; Hardware; Manufacturing; Shape; Space exploration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813337

Filename

813337