Title :
Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction
Author :
Cipriani, Stefano ; Duvivier, Eric ; Puccio, Gianni ; Carpineto, Lorenzo ; Bisanti, Biagio ; Coppola, Francesco ; Alderton, Martin ; Goldblatt, Jeremy
Abstract :
3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel stacking switch) chip. The 3 PLLs can work simultaneously synthesizing the same frequencies or different frequencies. To minimize the dynamic coupling among the PLLs a complete calibration algorithm has been implemented while to avoid static coupling a large use of differential structure and other design techniques have been used. The maximum composite spurious (due to PLLs coupling, Xtal spurious and fractional spurs) is -35 dBc (in +/-15 MHz range). Each PLL has a frequency range from 2.2 GHz to 4.4 GHz with a worst-case (over process and temperature) integrated rms of 1.2 deg at 3.8 GHz. The frequency step (31.25 KHz) is obtained with a 10 bit SD clocked at 32 MHz. The single PLL draw 35 mA from 3.8 Volt supply (regulated internally to 2.8 or 3.4 Volt) for 3.2 mm2.
Keywords :
BiCMOS integrated circuits; charge pump circuits; phase locked loops; satellite communication; BiCMOS; channel stacking switch; charge pump; current 35 mA; frequency 2.2 GHz to 4.4 GHz; frequency coupling; satellite communications; size 0.35 mum; triple SD PLL; voltage 3.8 V; Algorithm design and analysis; BiCMOS integrated circuits; Calibration; Cascading style sheets; Delta-sigma modulation; Frequency synthesizers; Phase locked loops; Stacking; Switches; Temperature distribution; BiCMOS; CSS; Charge pump; PLL; Satellite communications; Sigma delta; VCO; Xtal; calibration algorithm; frequency coupling;
Conference_Titel :
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European
Conference_Location :
Edinburgh
Print_ISBN :
978-1-4244-2361-3
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2008.4681868