DocumentCode :
349178
Title :
A VLSI architecture for fast and accurate floating-point sine/cosine evaluation
Author :
Paliouras, V. ; Karagianni, K. ; Stouraitis, T.
Author_Institution :
VLSI Design Lab., Patras Univ., Greece
Volume :
1
fYear :
1998
fDate :
1998
Firstpage :
473
Abstract :
A VLSI architecture is presented, combining floating-point and simple fixed-point arithmetic. The algorithm implemented by the architecture is based on second-order polynomial interpolation. The exploitation of certain properties of the trigonometric functions and of specific bit patterns which appear in the involved computations, has led to a 40% memory size reduction and low overall hardware complexity. The time required to evaluate a sine is less than the time required for three single-precision floating-point MACs, while the computed sines and cosines are guaranteed to be accurate to half an ulp (unit in last position)
Keywords :
VLSI; fixed point arithmetic; floating point arithmetic; interpolation; multiplying circuits; VLSI architecture; bit patterns; fixed-point arithmetic; floating-point sine/cosine evaluation; hardware complexity; second-order polynomial interpolation; trigonometric functions; Computer architecture; Design engineering; Fixed-point arithmetic; Hardware; Interpolation; Laboratories; Partitioning algorithms; Polynomials; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
Type :
conf
DOI :
10.1109/ICECS.1998.813365
Filename :
813365
Link To Document :
بازگشت