Title :
A high-speed parallel DSP architecture dedicated to digital modem applications
Author :
Philip, S. ; Monteiro, F. ; Dandache, A. ; Lepley, B.
Author_Institution :
LICM/CLOES/SUPELEC, Metz Univ., France
Abstract :
This paper presents the architecture of a high-speed digital signal processor (DSP) designed for high rate digital modem applications. This work stands as a part of an EURICO European project, whose target is the design of a TV cable modem. First, some aspects of the TV cable digital modem application are presented. Then, the paper describes the DSP architecture, based on a VLIW core processor and on auxiliary dedicated modules (ADM). The architectural choices and the main advantages are discussed. Last, the general structure of the ADMs is discussed through an example: the implementation of a cyclic redundancy checking (CRC) dedicated ADM
Keywords :
cable television; digital signal processing chips; high-speed integrated circuits; modems; parallel architectures; redundancy; EURICO European project; TV cable modem; VLIW core processor; auxiliary dedicated modules; cyclic redundancy checking; digital modem applications; high-speed parallel DSP architecture; Add-drop multiplexers; Cable TV; Computer architecture; Cyclic redundancy check; Digital signal processing; Hardware; Modems; Power cables; Prototypes; VLIW;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.813366
