Title :
A fractional spur reduction technique for RF TDC-based all digital PLLs
Author :
Wang, Ping-Ying ; Chang, Hsiang-Hui ; Zhan, Jing-Hong Conan
Author_Institution :
MediaTek Inc., Hsinchu
Abstract :
In this paper, a technique is proposed to suppress the fractional spur induced by non-linearity of the loop in all digital PLLs (ADPLLs). The measurement results show that the fractional spurs are reduced by at least 9 dB, to below -75 dBc, when the technique is applied to a conventional all digital PLL (ADPLL) at 3.6 GHz. The extra silicon area needed for technique is only 0.02 mm2.
Keywords :
digital integrated circuits; integrated circuit measurement; phase locked loops; all digital PLL; fractional spur reduction technique; frequency 3.6 GHz; 1f noise; Capacitance; Charge pumps; Digital control; Digital filters; Digital-controlled oscillators; MOS capacitors; Phase locked loops; Quantization; Radio frequency; ADPLL; Digital Controlled Oscillator (DCO); Spur; Time-to-Digital Converter (TDC);
Conference_Titel :
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European
Conference_Location :
Edinburgh
Print_ISBN :
978-1-4244-2361-3
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2008.4681882
