A 1.2-V, 600-MS/s, 2.4-mW DAC for WLAN 802.11 and 802.16 Wireless Transmitters

Author

Ghittori, N. ; Vigna, A. ; Malcovati, Piero ; D´Amico, S. ; Baschirotto, Andrea

Author_Institution

Dept. of Electron., Pavia Univ.

fYear

2006

fDate

Sept. 2006

Firstpage

404

Lastpage

407

Abstract

For the present and up-coming WLAN applications (802,11a/g, 802.11n, 802.16), a transmission baseband architecture uses a 600-MS/s current-steering DAC with a passive output load to perform the baseband signal processing, avoiding the use of any active reconstruction filter. In a 0.13-mum CMOS technology the DAC consumes 2.4 mW from a single 1.2-V supply voltage. The DAC exhibits a full-scale SFDR of 68 dB for an input signal frequency of 12 MHz and a full-scale dynamic range of 9.7 bits between 0 and 10 MHz. These data correspond to the best reported figure of merit, if compared with state-of-the-art digital-to-analog converters

Keywords

CMOS integrated circuits; active filters; digital-analogue conversion; radio transmitters; signal processing; wireless LAN; 0.10 MHz; 0.13 micron; 1.2 V; 12 MHz; 2.4 mW; 802,11a/g; 802.11; 802.11n; 802.16; 9.7 bit; CMOS; WLAN; active reconstruction filter; baseband signal processing; digital-to-analog converters; transmission baseband architecture; wireless transmitters; Active filters; Baseband; CMOS technology; Dynamic range; Frequency; Passive filters; Signal processing; Transmitters; Voltage; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European

Conference_Location

Montreux

ISSN

1930-8833

Print_ISBN

1-4244-0303-0

Type

conf

DOI

10.1109/ESSCIR.2006.307616

Filename

4099789