Title :
Improving design efficiency by providing models for simulation of parasitic effects of passive devices
Author :
Plathner, B. ; Kemper, U. ; Montiel, R. ; Brandstetter, M. ; Werker, H.
Author_Institution :
Semicond. Div., Siemens AG, Munich, Germany
Abstract :
Due to the rapidly decreasing device dimensions parasitic effects determined by the geometry of individual devices become more and more relevant. This paper describes how parasitic effects can be considered in an early design stage by developing passive models and taking into account geometrical and process specific data. The modeling concept, implementation and an application example is presented
Keywords :
CMOS analogue integrated circuits; circuit layout CAD; circuit simulation; integrated circuit layout; network parameters; parameter estimation; CMOS technology; analogue circuits; circuit simulation; design efficiency; device dimensions; geometrical data; parasitic effects; passive devices; process specific data; CMOS analog integrated circuits; CMOS process; CMOS technology; Circuit simulation; Geometry; Integrated circuit interconnections; Parasitic capacitance; Resistors; Semiconductor device modeling; Solid modeling;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.813374
