An FPGA synthesis of the distributed control systems designed with Petri nets

The paper describes a new method for the synthesis of the application specific distributed control systems, constructed using the FPGA devices. The initial steps of the proposed control algorithm rely on the notion of a Petri net, which is an easy way to describe parallel processes. The subsequent steps of the algorithm consist in the decomposition of a given Petri net - with the use of a coloring algorithm - into a set of state machine type subnets. We think of each subnet as representing one parallel process. These subnets are then implemented independently in different FPGA devices. To ensure proper communication between all subnets, the entire control system uses a globally asynchronous locally synchronous (GALS) architecture with each subnet synchronized by the local clock signal. Global communication between components is buffer-based and uses additional signals, generated in a given subnet and distributed to the remaining ones.