An investigation of the effect of synapse transfer characteristic on the performance of analogue neural networks

Much of the silicon area of an analogue neural network is consumed by the synapse circuits. It is therefore important to minimise the area of the synapses; however, it requires a high transistor count to implement a synapse circuit which has a good linearity over a wide operating range. The area of the synapse circuits can be reduced by employing a very simple three transistor circuit, but this is achieved at the cost of a loss of linearity of the synaptic multipliers. This paper presents an investigation of the impact of synapse nonlinearity on the learning power of the network. In some cases learning performance is severely compromised. A novel modification to the synapse circuits is suggested that is capable of alleviating the problems caused by synapse nonlinearity