A Delay-Locked Loop using a Synthesizer-based Phase Shifter for 3.2 Gb/s Chip-to-Chip Communication

A delay-locked loop in 0.18-mum CMOS for chip-to-chip communication at 3.2 Gb/s is presented. By leveraging the fractional-N synthesizer technique, this architecture provides fine-resolution and infinite-range delay and is less sensitive to process, temperature, and voltage variations than that of conventional techniques using a phase interpolator. A key element of the proposed structure is a digital Sigma-Delta modulator architecture that allows a high clock rate with compact area and reasonable power dissipation. The custom prototype IC operates at a 1.8-V supply voltage with a current consumption of 55 mA. The phase resolution is 1.4deg and measured differential and single-ended rms clock jitter is 3.6 ps and 4.8 ps, respectively. The core circuits occupy 0.42 mm²