A 6-10 bits Reconfigurable 20MS/s Digitally Enhanced Pipelined ADC for Multi-Standard Wireless Terminals

Author

Audoglio, Walter ; Zuffetti, Everest ; Cesura, Giovanni ; Castello, Rinaldo

Author_Institution

Studio di Microelettronica, STMicroelectronics, Pavia

fYear

2006

fDate

19-21 Sept. 2006

Firstpage

496

Lastpage

499

Abstract

A 20MS/s pipelined ADC architecture can be reconfigured in 10 clock cycles to resolve 6, 8, 9 or 10 bits at maximum resolution. A 9.1bit ENOB and 74dB SFDR with a power consumption of only 8mW was achieved by using background digital calibration and op-amp sharing techniques. The test chip, containing two ADC for I and Q processing within a wireless receiver, has been realized in a 0.13mum pure CMOS technology and uses 3.2mm² silicon area

Keywords

CMOS digital integrated circuits; analogue-digital conversion; operational amplifiers; 0.13 micron; 6 to 10 bit; 8 mW; CMOS technology; analog-to-digital converter; background digital calibration; multistandard wireless terminals; op-amp sharing techniques; reconfigurable digitally enhanced pipelined ADC; wireless receiver; Bandwidth; CMOS technology; Calibration; Energy consumption; Error correction; Operational amplifiers; Physical layer; Quality of service; Signal resolution; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European

Conference_Location

Montreux

ISSN

1930-8833

Print_ISBN

1-4244-0303-0

Type

conf

DOI

10.1109/ESSCIR.2006.307498

Filename

4099812