A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers

Author

Borghetti, F. ; Nielsen, J.H. ; Ferragina, V. ; Malcovati, P. ; Andreani, P. ; Baschirotto, A.

Author_Institution

Dept. of Electr. Eng., Pavia Univ.

fYear

2006

fDate

Sept. 2006

Firstpage

500

Lastpage

503

Abstract

A 10bit SAR-ADC implemented in a 1.2V 0.13mum CMOS with 1V_ppdiffFS, based on capacitive-charge redistribution can be programmed with F_s up-to-6MS/s, guaranteeing an ENOB>9b with a SFDR>74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoMap1pJ/conv. Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200muW and the FoMap0.1pJ/conv. This appears an attractive solution for embedded ADC

Keywords

CMOS digital integrated circuits; analogue-digital conversion; buffer circuits; programmable circuits; reference circuits; 0.13 micron; 1.2 V; 10 bit; CMOS integrated circuits; analog-to-digital converter; capacitive-charge redistribution; constant-FoM; on-chip reference voltage buffers; programmable SAR-ADC; CMOS technology; Capacitors; Circuits; Energy consumption; Frequency; Logic arrays; Parasitic capacitance; Sampling methods; Switches; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European

Conference_Location

Montreux

ISSN

1930-8833

Print_ISBN

1-4244-0303-0

Type

conf

DOI

10.1109/ESSCIR.2006.307499

Filename

4099813