DocumentCode
3492264
Title
On the influence of arithmetic underflow rounding standard on the speed of FDTD modeling
Author
Sypniewski, Maciej ; Gwarek, Wojciech K.
Author_Institution
Inst. of Radioelectronics, Warsaw Univ. of Technol., Poland
Volume
3
fYear
2004
fDate
6-11 June 2004
Firstpage
1795
Abstract
This paper presents the influence of arithmetic underflow rounding operations on the speed of FDTD analysis. It is shown that the underflow treatment according to the IEEE standard 754 (commonly accepted and implemented in modern arithmetic processors) may sometimes result in drastic slowdown of the speed of computing. The effect is much more pronounced in some of the most modern and most used processors. The ways to circumvent the effect by specific software operations are discussed.
Keywords
IEEE standards; computational electromagnetics; finite difference time-domain analysis; floating point arithmetic; FDTD modeling; IEEE standard 754; arithmetic processors; arithmetic underflow rounding standard; computing speed; floating point arithmetic; software operations; underflow treatment; Circuit simulation; Circuit testing; Computational modeling; Finite difference methods; Floating-point arithmetic; Microwave antennas; Microwave circuits; Microwave theory and techniques; Modems; Time domain analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Symposium Digest, 2004 IEEE MTT-S International
ISSN
0149-645X
Print_ISBN
0-7803-8331-1
Type
conf
DOI
10.1109/MWSYM.2004.1338949
Filename
1338949
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