DocumentCode :
349227
Title :
High-radix CORDIC for vector rotation with pipelined FPGA implementation
Author :
Kantabutra, Vitit
Author_Institution :
Dept. of Math., Idaho State Univ., Pocatello, ID, USA
Volume :
2
fYear :
1999
fDate :
5-8 Sep 1999
Firstpage :
1131
Abstract :
We present a new, mixed-radix (radix-4/radix-2) CORDIC algorithm for vector rotation and an efficient, pipelined implementation in Atmel´s AT40K technology. Using only 3 radix-4 stages and one radix-2 stage, a sample rotator using this new algorithm achieves in 4 clock cycles the same accuracy that a conventional (radix-2) rotator would achieve in 7 cycles, while each cycle is almost the same speed as that of a conventional rotator. This sample rotator attains 12 bits of accuracy externally, while internally 17 bits of accuracy is kept. This rotator fits in an AT40K30, and has a worst-case delay of up to 55.9 ns per stage (speed level 2) and a typical delay of 35 ns including output buffers. CORDIC rotators can be used to improve the efficiency of many important DSP functions such as transforms, modulation and demodulation, motion sensing and control, and image processing
Keywords :
clocks; delays; demodulation; digital arithmetic; field programmable gate arrays; pipeline processing; signal processing; 12 bit; 17 bit; 35 ns; 55.9 ns; Atmel AT40K technology; DSP functions; clock cycles; demodulation; high-radix CORDIC; image processing; motion sensing; output buffers; pipelined FPGA implementation; sample rotator; typical delay; vector rotation; worst-case delay; Clocks; Computational modeling; Delay; Demodulation; Digital signal processing; Field programmable gate arrays; Mathematics; Motion control; Signal processing algorithms; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
Type :
conf
DOI :
10.1109/ICECS.1999.813433
Filename :
813433
Link To Document :
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