Efficient implementation of embedded zero-tree wavelet encoding

Wavelet-based image compression algorithms tend to make intensive use of the system´s memory resources and its available access bandwidth. We propose a power efficient and fully pipelined software implementation on a generic processor platform of an embedded zero-tree wavelet encoder. The target processor class only has to contain a reasonable set of registers, an on-chip memory hierarchy with at least one level of caches and an offchip main memory partition. Within the same real-time constraints, the power exploration resulting for the data memory hierarchy related power consumption is decreased by a factor of 7 in comparison to a classical implementation, involving a separate row-column wavelet transform followed by the original embedded zero-tree encoding