ESD equivalent circuits and simulations-effects on gate oxide breakdown/degradation

ESD protection has been and still is one of the most important considerations in the design of CMOS devices. This is particularly crucial as we shrink transistor dimensions. Knowledge of the ESD pulse in terms of voltage build-up at the transistor gates of internal circuitry is important if we are to eliminate and/or reduce ESD effects on gate oxide breakdown/degradation. In this paper, we describe the modeling of the I/O protection circuitry which is an ESD protection device into equivalent circuits, as seen by a Human Body Model (HBM) ESD pulse. SPICE simulations are also performed