Hardware implementations of Gaussian elimination over GF(2) for channel decoding algorithms

In this paper, we investigate hardware implementations for Gaussian elimination of binary matrices. Gaussian elimination over GF(2) is a key operation used in several new channel decoding algorithms, that can provide large improvement of frame error rate over currently used algorithms. We first apply state-of-the-art architectures for binary Gaussian elimination to decoding algorithms. Then, we present a new hardware architecture, that has considerably less resource utilization and a higher throughput than state-of-the-art solutions. The designs have been implemented and compared on a Virtex 7 FPGA.