Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET

Author

Wambacq, Piet ; Verbruggen, Bob ; Scheir, Karen ; Borremans, Jonathan ; De Heyn, V. ; Van der Plas, G. ; Mercha, Abdelkarim ; Parvais, Bertrand ; Subramanian, Vaidy ; Jurczak, Malgorzata ; Decoutere, Stefaan ; Donnay, Stéphane

Author_Institution

IMEC, Leuven

fYear

2006

fDate

19-21 Sept. 2006

Firstpage

53

Lastpage

56

Abstract

Scaling to 45 nm node and below might necessitate the use of new processing steps (e.g. new gate stacks) or new device concepts such as FinFETs. Although intrinsic transistor speed increases with scaling, some analog performance parameters tend to degrade. In this paper we show with experimental results and simulations on analog and RF circuits that for high-speed and RF applications, downscaling to 45 nm channel length of bulk devices still improves RF circuit performance, while for low-frequency, high-gain applications FinFET technology offers better circuit performance than planar bulk CMOS

Keywords

CMOS integrated circuits; MOSFET; analogue integrated circuits; high-speed integrated circuits; radiofrequency integrated circuits; 45 nm; CMOS; FinFET; RF applications; RF circuits; analog circuits; channel length; high speed applications; intrinsic transistor; Analog circuits; CMOS analog integrated circuits; CMOS process; CMOS technology; Capacitance; Circuit optimization; Circuit simulation; FinFETs; Leakage current; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Conference_Location

Montreux

ISSN

1930-8876

Print_ISBN

1-4244-0301-4

Type

conf

DOI

10.1109/ESSDER.2006.307636

Filename

4099854