A High Performance pMOSFET with Two-step Recessed SiGe-S/D Structure for 32nm node and Beyond

Author

Yasutake, N. ; Ishida, T. ; Ohuchi, K. ; Aoki, N. ; Kusunoki, N. ; Mori, S. ; Mizushima, I. ; Morooka, T. ; Yahashi, K. ; Kawanaka, S. ; Ishimaru, K. ; Ishiuchi, H.

Author_Institution

Center for Semicond. Res. & Dev. Process, Toshiba Corp. Semicond. Co., Kanagawa

fYear

2006

fDate

19-21 Sept. 2006

Firstpage

77

Lastpage

80

Abstract

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe -source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved comparing with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451muA/mum at verbar;V_dd| of 0.9V, I_off of 100 nA/mum (552 muA/mum at |V_dd | of 1.0V). Furthermore, by combining with V_dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation

Keywords

Ge-Si alloys; MOSFET; nanotechnology; 15 nm; 24 nm; 32 nm; SiGe; drain current drivability; hole mobility; pMOSFET; short channel effect; source-drain structure; Capacitive sensors; Character generation; Degradation; Germanium silicon alloys; MOSFET circuits; Semiconductor device manufacture; Shape control; Silicon germanium; Strain control; Stress control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Conference_Location

Montreux

ISSN

1930-8876

Print_ISBN

1-4244-0301-4

Type

conf

DOI

10.1109/ESSDER.2006.307642

Filename

4099860