Title :
Dual phase TOSI-gate process on High-K dielectrics in a CMP-less flow
Author :
Mondot, A. ; Müller, M. ; Talbot, A. ; Vizioz, C. ; Pokrant, S. ; Leverd, F. ; Martin, F. ; Leroux, C. ; Morand, Y. ; Descombes, S. ; Aimé, D. ; Allain, F. ; Besson, P. ; Skotnicki, T.
Author_Institution :
STMicroelectronics, Crolles
Abstract :
In this paper, we demonstrate for the first time a new original approach of the integration of dual phase totally silicided (TOSI) gates using a close-to-standard CMOS flow without any additional CMP step targeting the use of NiSi for NMOS and Ni2Si for the PMOS gate electrode on high-k dielectrics. The impact of the TOSI-process on the gate stack characteristics is investigated in detail on capacitance, gate leakage and work function data. With respect to poly-Si gated devices we find a significant reduction of the effective oxide thickness in inversion without degradation of the gate leakage statistics. The results emphasize the potential of the integration of TOSI-gates on high-k gate oxides
Keywords :
MOSFET; capacitance; high-k dielectric thin films; leakage currents; nickel compounds; CMOS flow; CMP-less flow; NMOS gate electrode; Ni2Si; NiSi; PMOS gate electrode; capacitance; dual phase totally silicided gates; effective oxide thickness; gate leakage; gate stack characteristics; high-k dielectrics; poly-Si gated devices; work function; CMOS process; Electrodes; Fabrication; Gate leakage; High K dielectric materials; High-K gate dielectrics; MOS devices; Silicidation; Silicides; Statistics;
Conference_Titel :
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0301-4
DOI :
10.1109/ESSDER.2006.307652
