Author :
Fenouillet-Beranger, C. ; Gallon, C. ; Vandooren, A. ; Aime, D. ; Tosti, L. ; Leverd, F. ; Faynot, O. ; Arvet, C. ; Perrot, C. ; Froment, B. ; Müller, M. ; Allain, F. ; Toffoli, A. ; Vanbergue, S. ; Villani, M.L. ; Delille, D. ; Pokrant, S. ; Skotnicki, T
Abstract :
This paper presents a study of the integration of a TOSI gate process on fully-depleted SOI devices by using a CMP-less approach and a detailed electrical characterization of NMOS and PMOS transistors, including transport properties. Tuning of the workfunction has been observed for the NMOS devices by doping the polysilicon before gate silicidation. Functional PMOS and NMOS devices have been tested down to 50nm gate length. PMOS devices exhibits very good Ion/Ioff performances (Ion: 492muA/mum at Ioff: 25nA/mum @ Vdd -1.2V) despite the relatively thick gate oxide thickness used. The inverters´ functionality of the FDSOI SRAM cell with a size of 0.99mum2 has also been demonstrated, reflecting that this technology is a very promising candidate for 45nm LP node and beyond
Keywords :
MOSFET; SRAM chips; field effect devices; semiconductor doping; silicon-on-insulator; transport processes; -1.2 V; 45 nm; FDSOI SRAM cell; NMOS transistor; PMOS transistor; inverter functionality of; totally silicided gate integration; transport properties; ultra-thin film FDSOI devices; Annealing; Dielectrics; Doping; Epitaxial growth; Fabrication; MOS devices; MOSFETs; Nickel; Silicidation; Silicon;
