First ultra-thin film FDSOI devices with CMP-less TOtally SIlicided (TOSI) gate Integration

Author

Fenouillet-Beranger, C. ; Gallon, C. ; Vandooren, A. ; Aime, D. ; Tosti, L. ; Leverd, F. ; Faynot, O. ; Arvet, C. ; Perrot, C. ; Froment, B. ; Müller, M. ; Allain, F. ; Toffoli, A. ; Vanbergue, S. ; Villani, M.L. ; Delille, D. ; Pokrant, S. ; Skotnicki, T

Author_Institution

CEA-LETI, Grenoble

fYear

2006

fDate

Sept. 2006

Firstpage

158

Lastpage

161

Abstract

This paper presents a study of the integration of a TOSI gate process on fully-depleted SOI devices by using a CMP-less approach and a detailed electrical characterization of NMOS and PMOS transistors, including transport properties. Tuning of the workfunction has been observed for the NMOS devices by doping the polysilicon before gate silicidation. Functional PMOS and NMOS devices have been tested down to 50nm gate length. PMOS devices exhibits very good Ion/Ioff performances (Ion: 492muA/mum at Ioff: 25nA/mum @ Vdd -1.2V) despite the relatively thick gate oxide thickness used. The inverters´ functionality of the FDSOI SRAM cell with a size of 0.99mum² has also been demonstrated, reflecting that this technology is a very promising candidate for 45nm LP node and beyond

Keywords

MOSFET; SRAM chips; field effect devices; semiconductor doping; silicon-on-insulator; transport processes; -1.2 V; 45 nm; FDSOI SRAM cell; NMOS transistor; PMOS transistor; inverter functionality of; totally silicided gate integration; transport properties; ultra-thin film FDSOI devices; Annealing; Dielectrics; Doping; Epitaxial growth; Fabrication; MOS devices; MOSFETs; Nickel; Silicidation; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Conference_Location

Montreux

ISSN

1930-8876

Print_ISBN

1-4244-0301-4

Type

conf

DOI

10.1109/ESSDER.2006.307662

Filename

4099880