Optimization of ESD protection device using SCR structure of a novel STI-sided LDMOS with P-top layer for 5 V operating voltage

In this paper, comparison between original and Silicon Controlled Rectifier (SCR) structure of a novel Shallow Trench Isolation (STI)-sided LDMOS with P-top layer is firstly presented. SCR structure can be used as a robust Electrostatic Discharge (ESD) protection device as its failure current (It2) is five times higher compared to original structure. This high It2 also results in optimizing of device width as the hot spot area is wider. The low holding voltage (Vh) of SCR structure is optimized by increasing the doping concentration of P-Body to minimize the risk of induced latch-up. The modification of surface doping concentration is the best way to increase the Vh as the crowded current of SCR structure is placed under the channel and source region while maintaining It2 below ESD thermal failure.