DocumentCode :
3493511
Title :
Using UPPAAL to model and verify a clock synchronization protocol for the controller area network
Author :
Rodríguez-Navas, Guillermo ; Proenza, Julián ; Hansson, Hans
Author_Institution :
Dept. de Matematiques i Informatica, Univ. de les Illes Balears, Palma de Mallorca
Volume :
2
fYear :
2005
fDate :
19-22 Sept. 2005
Lastpage :
502
Abstract :
A reported liability of the controller area network protocol is that it does not provide a clock synchronization service. Therefore, whenever a CAN-based distributed embedded system requires its nodes to have a common time base, clock synchronization has to be implemented by means of an external mechanism. In a previous work, we proposed a fault-tolerant and high-precision clock synchronization protocol for CAN. This paper shows the first steps towards the formal verification of this protocol. In particular, it presents a formal model that has been built with the UPPAAL model checker and discusses how clock drift and clock correction can be modeled with this tool
Keywords :
controller area networks; embedded systems; fault tolerant computing; formal verification; protocols; synchronisation; CAN; UPPAAL model checker; clock synchronization protocol; controller area network; distributed embedded system; fault-tolerance; formal verification; Application software; Automata; Automatic control; Clocks; Electronic mail; Embedded system; Formal verification; Medical control systems; Protocols; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Emerging Technologies and Factory Automation, 2005. ETFA 2005. 10th IEEE Conference on
Conference_Location :
Catania
Print_ISBN :
0-7803-9401-1
Type :
conf
DOI :
10.1109/ETFA.2005.1612717
Filename :
1612717
Link To Document :
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