Analysis of IC fabrication processes using self-organizing maps

The analysis of integrated circuit (IC) fabrication processes is an important task in order to optimize the yield and to detect problems in very early state. Neural networks seem to be a promising approach to data analysis, especially when there is a large amount of data with many nonlinearities. In this paper we describe the use of self-organizing maps (SOM) for visualization and analysis of data derived from a running IC production of the Robert Bosch GmbH Waferfab at Reutlingen, Germany. The main aspects are techniques for pressure sensor trimming and online process monitoring for in-process data, parameters and the process status. After a short description of visualization techniques for SOM, we present the results based on the real world data from the Waferfab