Title :
Integrated VDMOS transistor with reduced JFET effect
Author :
Hakim, Hedi ; Bolognesi, Davide ; De Pestel, F.
Author_Institution :
AMI Semicond., Oudenaarde
Abstract :
In order to improve the trade-off between the breakdown voltage and the on-state resistance of integrated VDMOS transistors, an anti junction field effect implant has been introduced for an 80V smart power platform based on a 0.35 mum CMOS node. Optimized dose and energy allow a reduction of the resistance without significant impact on the breakdown voltage and the other integrated components of the technology
Keywords :
CMOS integrated circuits; MOSFET; junction gate field effect transistors; power integrated circuits; semiconductor device breakdown; 0.35 micron; 80 V; CMOS node; anti junction field effect implant; breakdown voltage; integrated VDMOS transistor; on-state resistance; reduced JFET effect; smart power platform; Ambient intelligence; BiCMOS integrated circuits; CMOS technology; Costs; FETs; Fabrication; Implants; Software performance; Topology; Voltage;
Conference_Titel :
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0301-4
DOI :
10.1109/ESSDER.2006.307692
