Title :
Fabrication and Analysis of CMOS Fully-Compatible High Conductance Impact-Ionization MOS (I-MOS) Transistors
Author :
Charbuillet, C. ; Dubois, E. ; Monfray, S. ; Bouillon, P. ; Skotnicki, Thomas
Author_Institution :
STMicroelectron., Crolles
Abstract :
This paper reports on a new process to realize impact-ionization MOSFETs (I-MOS) with gate length down to 50nm. This process is an adaptation of a standard 90nm flow, which assures a perfect compatibility with conventional CMOS. The definition of the n+ and p+ regions of the I-MOS is based on two shifted lithography steps using the standard source/drain mask. An analytical model for the breakdown voltage of an ID p-i-n diode has also been developed to express the breakdown voltage of I-MOS devices as a function of the gate and intrinsic lengths, and the doping level. This model has been validated by the experimental results. An extremely low experimental device resistance (270 Omega.mum) is reported at a gate length of 55 nm, placing the I-MOS architecture favorably with respect to ITRS requirements. This performance is explained by the much higher carrier concentration generated by impact ionization when compared to the conventional MOS. Channel resistance is found negligible and current only limited by the source/drain (S/D) resistance
Keywords :
CMOS integrated circuits; MOSFET; impact ionisation; masks; p-i-n diodes; semiconductor device breakdown; 90 nm; CMOS integrated circuit; I-MOS devices; ITRS requirements; MOSFET; breakdown voltage; high conductance transistor; impact-ionization MOS transistor; p-i-n diode; source/drain mask; source/drain resistance; CMOS process; Conducting materials; Fabrication; Impact ionization; Leakage current; Lithography; MOSFETs; P-i-n diodes; Silicon; Voltage;
Conference_Titel :
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European
Conference_Location :
Montreux
Print_ISBN :
1-4244-0301-4
DOI :
10.1109/ESSDER.2006.307697
