Co-integration of 2 mV/dec Subthreshold Slope Impact Ionization MOS (I-MOS) with CMOS

Author

Mayer, F. ; Le Royer, Cyrille ; Le Carval, Gilles ; Tabone, C. ; Clavelier, L. ; Deleonibus, S.

Author_Institution

CEA, Grenoble

fYear

2006

fDate

Sept. 2006

Firstpage

303

Lastpage

306

Abstract

The reduction of the subthreshold slope S in conventional MOSFETs hits against the diffusion phenomena which limits S to 60 mV/dec at 300K. This paper deals with a new type of device, the impact ionization MOSFET (I-MOS), which allows few mv/dec subthreshold slopes. For the first time, classical CMOS have been co-integrated with complementary I-MOS (CI-MOS) on silicon-on-insulator wafers (SOI). Using a standard CMOS process, we have obtained fully functional n & p MOSFETs, and n & p I-MOS with S respectively down to 6 and 2 mV/dec

Keywords

CMOS integrated circuits; MOSFET; impact ionisation; silicon-on-insulator; CMOS process; SOI wafers; complementary I-MOS; diffusion phenomena; impact ionization MOS; impact ionization MOSFET; n MOSFET; p MOSFET; silicon-on-insulator wafers; subthreshold slope; CMOS process; CMOS technology; Impact ionization; Isolation technology; Leakage current; MOSFETs; Resists; Semiconductor films; Silicon on insulator technology; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European

Conference_Location

Montreux

ISSN

1930-8876

Print_ISBN

1-4244-0301-4

Type

conf

DOI

10.1109/ESSDER.2006.307698

Filename

4099916